Packet processors are used in network devices to handle the routing of packets. Packet processors are typically implemented as RISC (Reduced Instruction Set Computers) processor. In some instances these packet processors are implemented as programmable/multithreaded devices. The key benefits of multi-threaded packet processors include simpler instruction execution pipeline eliminating pipeline hazards, resource conflicts, branch delays, pipeline stalls, and pipeline stage bypasses. Another advantage of these type of processors is they provide a simpler programming model by hiding memory access latencies, hiding coprocessor latencies, eliminating branch delays, removing operand dependencies, provide better utilization of available memory bandwidth and better utilization of coprocessors. To increase memory capacity and/or reduce cost, packet processors have made use of Reduced Latency Dynamic Random Access Memory (RLDRAM) and Synchronous Dynamic Random Access Memory (SDRAM).